1. Field of the Invention
The invention relates in general to a manufacturing method of forming a CMOS transistor, and more particularly to a manufacturing method of forming the source/drain and lightly doped region of a CMOS transistor using two procedures of implantation.
2. Description of the Related Art
While most thin film transistors used in flat displays are manufactured via amorphous silicon manufacturing process, only a few advanced products adopt polysilicon manufacturing process which has higher electron mobility. Polysilicon technology allows more electronic circuits to be integrated into, so the overall complexity and weight of product can be reduced. Since the highest temperature during polysilicon manufacturing process is over 300° C., a temperature far above the softening point of plastics, so this manufacturing process can only be applied to glass substrate.
Referring to FIG. 1A˜1I, diagrams showing a conventional manufacturing process of a low-temperature polysilicon thin film transistor. Firstly, in FIG. 1A, a buffer layer 102 and a polysilicon layer 104 are sequentially formed on a substrate 100, wherein the polysilicon layer is formed by using excimer laser to crystallization anneal the amorphous layer. Next, a patterned photoresist layer is formed (not shown here) and the polysilicon layer 104 as shown in FIG. 1A is formed thereafter by using the photoresist layer as a mask of etching process.
After that, referring to FIG. 1B, a gate oxide 108 is deposited over buffer layer 102 and polysilicon layer 104; a conductive layer is further formed over gate oxide 108. Gate 110 is then formed by using photolithography and etching process. Following that, in FIG. 1C, a photoresist layer 112 which covers up entire PMOS transistor region as well as the gate and lightly doped region of NMOS transistor is formed. Furthermore, photoresist layer 112 is used as mask and a high concentration phosphorus dopant is implanted to form the source/drain 104a, 104b, 104c, and 104d of NMOS transistor.
Following that, in FIG. 1D, the remnants of photoresist layer 112 are removed, gate 110 is used as mask directly, and a low concentration phosphorus dopant is implanted into substrate 100 to form the lightly doped regions 104m, 104n, 104x, and 104y of NMOS transistor. Next, in FIG. 1E, a photoresist layer 114 is formed again, wherein the photoresist layer 114, which covers up entire NMOS transistor region, is used as mask, and a high concentration boron dopant is implanted into substrate 100 to form the source/drain 104i and 104j of P-type transistor.
In FIG. 1F, first of all, the photoresist layer 104 is removed, an inner dielectric layer 116 is formed on gate 110 and gate oxide 108 with a plurality of openings are formed in inner dielectric layer 116 and gate oxide 108. Next, in FIG. 1G, an electrode 118 which can be electrically connected to source/drain 104a, 104b, 104c, 104d, 104i, and 104j is formed therein.
Next, in FIG. 1H, a passivation layer 120 is formed on electrode layer 118 and inner dielectric layer 116, wherein an opening is formed on passivation layer 120 of pixel region so that electrode 118 can be exposed. Lastly, in FIG. 1I, a transparent electrode 122 which can be electrically connected to electrode 118 of pixel region is formed so as to conclude the manufacturing process of low-temperature polysilicon thin film transistor.
The manufacturing process of low-temperature polysilicon thin film transistor according to the conventional technology requires eight photo-masking and three procedures of ion implantation, wherein the eight processes of masking are illustrated in FIG. 1A˜1C and FIG. 1E˜1I while the three procedures of ion implantation are illustrated in FIG. 1C˜1E. However, each manufacturing procedure adds to an increase in manufacturing cost. It is therefore an urgent need to reduce the required number of manufacturing procedures if the manufacturing cost is to be further cut down.